1. Field of the Invention
The invention relates to a method and system for dicing wafers of greater die strength, and semiconductor structures incorporating the products thereof.
2. Description of the Related Art
Thin semiconductor wafers have been separated into a plurality of diced chips by a number of conventional techniques including sawing, laser scribing, mechanical scribing and cleaving, and chemical etching and cleaving.
Referring to FIG. 1, the dicing of a wafer by sawing is illustrated in which a diamond saw blade 10 is shown with its rotational and lateral directions of motion indicated by arrows. The blade 10 has a forward entrance edge 14 cutting through the active (upper) face 12 of the semiconductor wafer 11 and an exit edge 15 at the back (bottom) side 13 of the wafer 11. Dicing striations 16 formed through the thickness of the wafer 11 by action of the sawing blade 10 are indicated. Referring now to FIGS. 2A and 2B, when a thin semiconductor wafer 10 is sawed in this manner, chipping results along the sawed edges due to the brittleness of the semiconductor. The source of damage on a diced chip 11 is the passage of the dicing blade 10 through the brittle semiconductor material, leaving microcracks and removed scallops of material along the diced edges. Such damage is not uniform, as the microcracks and scallops 21 formed on the entrance edge 14 of the chip 11 where the blade 10 enters the active wafer surface 12 are much smaller in size (e.g., about 2-3 .mu.m) than the microcracks and scallops 22 formed on the edge 15 of the chip 11 where the blade 10 exits the back-side surface 13 of wafer 11 (e.g., about 10-100 .mu.m).
The present investigators have determined that wafers diced in such a conventional manner with a sawing blade, e.g., a diamond saw, entering the active side, ordinarily faced up during the sawing, and exiting the non-active side, ordinarily faced down, whether by one or multiple blade passes, exhibit bi-modal chip-strength characteristics. That is, the chips flexed in bending such that the active face and diced edges are placed in tension show large strengths with little variability while those flexed such that the non-active face and diced edges are placed in tension show small strengths with large variability. Consequently, there is a connection between the damage introduced into the edges of a die as a consequence of dicing and the subsequent sustainable tensile stress or strength of the die. Small-scale damage is associated with large strength (strong chips or chip-edges, capable of sustaining large stresses) and large-scale damage is associated with small strength (weak chips or chip-edges, capable of sustaining only small stresses).
Furthermore, many packaging schemes place the back face of a chip into tension, or, at least, much more tension than the front face. This leads to loss of devices on packaging or expensive, more compliant package re-designs. There is thus a need for entrance-cut faces and edges to be placed on the faces and edges experiencing the maximum tension. This is not possible with conventional front face dicing, such as illustrated in FIG. Nos. 1, 2A-B. In cases in which the entire chip experiences significant tension, there is an analogous need for entrance cuts on both sets of edges, and, again this is not possible with conventional front face dicing.
U.S. Pat. Nos. 4,814,296 and 5,219,796 describe a v-shaped groove used in forming image sensor dies by dicing a silicon wafer. The v-shaped groove prevents cracks and chipping caused by dicing on the entrance side. The v-shaped groove described in these 4,814,296 and 5,219,796 patents is a special type of crack prevention structure that allows for dies that are going to be assembled together with butted edges with limited chipping. This represents a narrow purpose that does not necessarily require improved die strength. A wide groove is provided in the backside, apparently, so that a cut can be made from the top without having to be concerned about precise alignment when breaking through the back. The end result is a crack free and precise top surface, and no backside variations because the backside is cut away that would limit or effect how close the die could be butted together on the top surface. Also the U.S. Pat. Nos. 4,814,296 and 5,219,796 require making double parallel passes through the dicing "streets" in order to get minimum cracked surfaces on each adjoining die.
U.S. Pat. Nos. 4,721,977 and 4,900,283 teach a method for simultaneously dicing from both sides of a semiconductor wafer to obtain a beveled edge for making butted surfaces. From a practical standpoint, such a procedure described in U.S. Pat. Nos. 4,721,977 and 4,900,283 would be challenging insofar as establishing and maintaining proper registry of the opposing grooves formed by simultaneously sawing from opposing sides of the wafer.
U.S. Pat. No. 4,729,971 describes a die separation technique involving etching and other processing steps at thickened portions of a wafer to provide dice having straight and smooth diced edges. The extra processing required would be expected to entail high manufacturing costs.
As can be appreciated from the above discussions, the semiconductor industry would value a more facile technique to subdivide semiconductor wafers into dies possessing high die strength.
Another area where the conventional dicing technology has not been fully satisfactory or could be improved, as also identified by the present inventors, relates to semiconductor devices built with different technologies fabricated on separate wafers, diced, and then connected together by mounting one of the die on the other. For example, in certain packaging applications, the merging of dynamic random access memory (i.e., DRAM) and logic (as well as merging of other dissimilar technologies) has been headed towards connecting one chip directly to the face of another chip through controlled collapsed chip connection (i.e., C4) solder connections. A so-called "mother/daughter" chip structure has been used to provide a large number of inputs/outputs (i.e., I/O's) between two chips, although it can create limitations on the available area to make connections to the outside package.
As illustrated in FIG. 8A, in such mother/daughter chip configuration 803, the squared-off back side edges 804 on the diced wafer back (non-active) side 805 delimit the space available for wire bonding. The front (active) side 801 of the mother chip 81 is attached to the front (active) side 800 of the daughter chip 80 by solder (C4) 802. However, when wire bonding out off the mother chip 81 using wire bonder tip 82 to deposit a wire line on pad 84, the daughter chip 80 has to be sized small enough relative to the mother chip 81 to allow for a wire bonder tip 82 to come in closely adjacent the side edge 84 of the daughter chip 80 and form the wire bond 83 on the adjacent exposed ledge 806 on the front (active) side 801 of the mother chip 81. The end result has been a conventional mother/daughter chip structure 803 such as shown in FIG. 8A. This has entailed lateral sizing constraints on the daughter chip 80, which in turn resulted in reduced real estate available on the active side 800 of the daughter chip 80 for active circuits and/or I/O's 82 between the two chips 80 and 81.
Also, in the packaging of a diced chip or die unit by encapsulation, problems of limited die strength have been encountered heretofore. For instance, as illustrated in FIG. 9A, the encapsulated semiconductor package 900 includes lead frames 901 wirebonded to the active side 903 of IC silicon chip 904 to provide a die unit, and the die unit is encapsulated in rigid plastic 905, such as a cured silicone potting resin. The back (non-active) side 906 of the die unit has been diced by conventional methods to provide squared-off edges 907, which act as stress risers, which, in turn, tends to be a crack initiator causing failure cracks 908 in the plastic encapsulant 905.